1. Field of the Invention
This invention relates to computer circuitry and, more particularly, to handshake interface circuitry for connecting asynchronous components to a computer bus.
2. History of the Prior Art
The typical interface system for transferring information between two computer systems is a synchronous interface system, one which drives the two systems off the same clock. Joining the two systems is usually a data bus for carrying information, an address bus for carrying addresses, and various control lines including lines for accomplishing a so-called "handshake" between the two systems. Normally a write line, a read line, and an acknowledge line are required for transferring control signals between the two systems to accomplish the handshake.
In the normal synchronous interface where both computer systems are running on the same clock, a computer system wishing to write to a second system provides a write signal on the write line. The second system samples the write line connecting the two systems to detect the write signal and, in response to that signal, receives the data on the data bus and returns an acknowledge pulse on the acknowledge line to indicate that the data has been received. Each of the signals on the handshake lines is driven by the system clock and, in a preferred embodiment, occurs on the rising edge of the system clock pulse. Consequently, the handshaking operation in a synchronous system where the same clock controls both systems usually requires one clock period for the write signal to be driven onto the write line, and a second clock period for the second system to sense the appearance of the write signal on the write line and to acknowledge receipt of the information by placing the acknowledge signal on the acknowledge line. Moreover, before additional information may be written through the interface system, a third clock period is necessary to terminate the original write signal; and a fourth clock period is required to terminate the acknowledge signal. Consequently, a write handshake procedure in the normal synchronous computer interface may take as long as four clock periods.
At an asynchronous interface where the two systems joined by the bus operate at different clock frequencies, it is necessary that the incoming and outgoing handshake signals be synchronized to each of the two systems as they travel in each direction. Consequently, an incoming write signal must be synchronized to the clock of the receiving system while the outgoing acknowledge signal must be synchronized to the clock of the sending system. The normal manner in which this is accomplished by the prior art is to use two stages of flip-flops on each handshake line, each stage being driven by the clock of the system receiving the particular signal. An incoming signal causes the first stage flip-flop to begin switching; and, because of the timing differential between the clock pulse of the receiving system and the incoming signal, the first flip-flop may assume a metastable condition, erratically switching between states until finally settling into one of the two possible states. However, the final output of the first flip-flop causes the second flip-flop to take a state thereby isolating the dithering from the receiving system. The use of two stages of flip-flops to receive the handshake signals adds at least two additional clock periods to each step of the synchronization in an asynchronous interface of the prior art.
There have been asynchronous interface systems designed which utilize latches to receive the incoming information at the second system so that data may be immediately transferred between the systems without synchronization. However, such latches do not eliminate the need to synchronize the information to the clock of the receiving system but merely delay the time at which the synchronization of the information must occur. It merely moves the bottleneck from the interface circuitry to some later stage of the receiving system where, in fact, two stages of synchronization are still necessary before the data may be utilized.